Projects
& Work
A full-stack iOS app shipped solo to the App Store and FPGA verification tooling built at Synopsys.
App Store ✓
Synopsys intern
Finio · Technical Core
Python signal pipeline
Raw market data → filtered features → AI verdict. The same pattern as embedded DSP — just in Python instead of C.
01 INPUT
Raw OHLCV
Polygon.io bars + Finnhub live quotes
2 sources
02 FILTER
Rolling avg · Z-norm
60-period window, z-score normalization
NumPy
03 FEATURES
4 signal channels
Momentum · Volatility · Volume · EMA cross
4 channels
04 VERDICT
Buy / Hold / Sell
AI-generated analyst output → Firebase → iOS
Live
# momentum: rate of change
roc = (close - close.shift(20)) / close.shift(20)
# normalize to z-score
z = (roc - roc.rolling(60).mean()) / roc.rolling(60).std()
Finio · Architecture
Finite state machine design
App session logic modelled as a FSM — same pattern as USB-PD negotiation or a diagnostic firmware handshake.
Finio FSM
MARKET_OPEN
signals active
POSITION_ACTIVE
user holds
ORDER_PENDING
sell submitted
USB-PD parallel
CAP EXCHANGE
buy_confirmed()
CONTRACT NEG.
sell_request()
FIRESTORE INTERRUPT PATTERN
Firestore listeners fire on change — structurally interrupt-driven. Fault recovery: rate-limit hit → cache fallback → stale flag. No silent failures.
Synopsys · FPGA Prototyping Team
Synthesis Regression Automation
Python + TCL tooling that dynamically extracted net-level properties across 300+ Synplify regression testcases — eliminating brittle hardcoded checks that broke on net name changes.
The problem
- Regression checks hardcoded net names like
en1_0 — any synthesis tool change silently broke them
- Fanout report generation required UI invocation, causing batch-mode failures across suites
- 300+ Xilinx + Altera testcases had stale
check.dat logic with no scalable fix
What I built
- TCL script traversing all flops via
get_prop clock_enable, dynamically resolving enable net names at runtime
- Python script validating fanout values against the extracted net — replacing all hardcoded string checks
- Fixed
open_file → open_design in fanout TCL enabling batch-mode log generation without UI
- Verilog testbench toggling enable signals, comparing RTL vs synthesized outputs in Verdi
Stack
Python
TCL
Verilog / Verdi
Synplify Pro
Synopsys HAPS
Outcome
300+ testcases · 0 failures
"Functional and sophisticated" — Hari Haran, Synopsys